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ARM Architecture Reference Manual 13.04.09, 16:21 Автор Anton Gerasimov список файлов: ARM Architecture Reference Manual.pdf ARM prt 0 0 комментариев Automatic Layout Modification Including Design Reuse of the Alpha CPU in 0.13 um SOI Technology Reading 31.03.09, 16:47 Автор Anton Gerasimov список файлов: Automatic Layout Modification Including Design Reuse of the Alpha CPU in 0.13 um SOI Technology (Reinhardt - 2002).pdf prt 0 0 комментариев On-Chip Communication Architectures-System on Chip Interconnect Networks-on-a-Chip (NoC) 29.03.09, 15:06 Автор Anton Gerasimov список файлов: On-Chip Communication Architectures-System on Chip Interconnect.pdf on-chip bus prt 0 0 комментариев Static Timing Analysis Based Transformations of Super-Complex Design Flow 08.03.09, 22:19 Автор Anton Gerasimov http://etd.library.pitt.edu/ETD/available/etd-03102008-120235/unrestricted/ColinIhrig-ms-3-18-08.pdf hdlin_enable_presto_for_vhdl = true analyze -format vhdl delay_vhd elaborate delay_4_0 current_design delay_4_0 set_combinational_type -replacement_gate ... список файлов: ColinIhrig-ms-3-18-08.pdf Pittsburgh prt hdlin_enable_presto_for_vhdl DC Compiler STA 0 0 комментариев Voltage Drop Analysis Design Flow 08.03.09, 19:33 Автор Anton Gerasimov http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2003/iccad03/pdffiles/10a_3.pdf http://synopsysoc.org/magicbluesmoke/wp-content/uploads/2007/11/stringfellow_final.pdf список файлов: AstroRail.jpg testrail.jpg AstroRail2.jpg stringfellow_final.pdf 10a_3.pdf saleh_final.pdf DESIGN_AUTOMATION.pdf Voltage Drop TestRail AstroRail Synopsys prt 0 0 комментариев DRAM Circuit Design MEMORY 06.03.09, 14:59 Автор Anton Gerasimov список файлов: dram.jpg DRAM Circuit Design A Tutorial.pdf DRAM SDRAM prt circuit design 0 0 комментариев Topological Synthesis of Clock Trees Design Flow 05.03.09, 15:47 Автор Anton Gerasimov http://www.ece.rochester.edu/users/friedman/papers/Tau_97.pdf Clock Tree prt Topological Synthesis 0 0 комментариев STNoC Total Networks-on-a-Chip (NoC) 03.03.09, 11:31 Автор Anton Gerasimov список файлов: stnoc.jpg stnoc2.jpg Design_of_Cost_Efficient_Interconnect_Processing_Units_Spidergon_STNoC.Sep.2008.eBook-DDU.pdf mrc_241.pdf STNoC Spidergon prt 0 0 комментариев ASIC Optimization and Design Strategy Using Multiple Vt Devices Power-Management 28.02.09, 19:35 Автор Anton Gerasimov http://www.cdnusers.org/community/encounter/resources/resources_lp/tp_1361_ibmppt.pdf http://www.cedb.gov.hk/citb/psdas/content/doc/2003-1-10/WS1-Presentation.pdf список файлов: WS1-Presentation.pdf tp_1361_ibmppt.pdf optLeakagePower Cadence RTL Compiler prt 0 0 комментариев Multi-Clock Domain (Verifying Synchronization) Design Practice 21.02.09, 23:07 Автор Anton Gerasimov http://www.cs.huji.ac.il/~jarom/vlsi_seminar/Papers/CDC_DVCon.pdf список файлов: hdl_designer.jpg CDC_DVCon.pdf clock domain HDL Designer Mentor Synchronization prt 0 0 комментариев Вперёд 1 2		Рубрики сообщества Design Flow (67) Multicore (5) News (12) Education (9) Patents (4) Multi-cores (3) Networks-on-a-Chip (NoC) (44) Singapore (7) Reading (213) VLIW (5) TLM-Modeling (2) Google (19) Intel (20) Trainings (19) SystemC (18) Mentor Graphics (2) Network processors (2) 65 nm (5) IEEE (2) STMicroelectronics (18) Verification (18) Protocol Design and Analysis (6) CAD (13) Pattern Recognition (1) HDTV Design (6) Projects (3) Functional Programming (1) МФТИ (2) IP Blocks (3) LOGIC Design (16) Conferences (2) ARCH (67) Power-Management (28) CHINA/Китай (4) Реальные инновации (0) Fabs/ Production (13) Fundings (2) Crolles2 (1) 45 nm (4) Algorithms Analysis/ Optimization (1) IC Design People (6) FSA (Fabless Semiconductor Association) (2) Optimization (18) FPGA (7) SW (Embedded Software) (31) RF/ Analog Design (3) Project Control (1) НИИСИ РАН (5) VIRTUALIZATION (6) C++ (3) 32 nm (1) Simulation (10) Design Gotchas (7) Parallel Programming (1) Chipset Design (2) MEMORY (20) Design Practice (7) LIB Design (2) Все (827) Участники Anton Gerasimov loktikvj svtemp chernyatiev Всего 48 участников Облако тегов 45nm 65nm AMBA AMD ARM Asynchronous BIST Branch Prediction Cache Cadence clock domain Cortex DDR DFT DRAM fabless Fabless Design HDTV IBM Intel ISS Low-Power Mailbox MapReduce Mentor Microcode Network Processor NoC noc OCCN Optimization PLL PrimeTime prt RTL RTOS SNUG STA STMicroelectronics Synopsys Synthesis SystemC SystemVerilog TLM TSMC Verification Verilog Verilog PLI Virtualization VLIW Ближайшие события февраль 2021 Пн Вт Ср Чт Пт Сб Вс 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28