RuChip is developing the SMP version of its GOYA core.
This architecture extension is based on a snooping mechanism that exploits the well know MESI protocol, with the aim to leverage the current GOYA implementation and adding to it the capability to support an SMP sub-systems or more simply just to support cache coherency. The target is SoC platforms with a small number of processors that share a coherent memory address space.
The approach described in this document is based on memory coherency managed at the L1 data cache interface with an option of an L2 cache shared between processors to maximize the expected benefits in terms of latency and bandwidth saving/traffic reduction on the system bus, but leaving the choice to use whatever memory hierarchy free for the SoC architect to make. The snooping interconnect defined here can be applied unchanged to different memory hierarchies, the snooping mechanism will remain the same. For example, a coherent multi level private cache subsystem will add complexity to the cache controllers but the unit which manages memory coherency will not be affected by it. This is a desirable property that allows this approach and a big part of the design that’ll come with it to be leveraged for future spins of the GOYA architecture.
45nm 65nm AMBA AMD ARM Asynchronous BIST Branch Prediction Cache Cadence clock domain Cortex DDR DFT DRAM fabless Fabless Design HDTV IBM Intel ISS Low-Power Mailbox MapReduce Mentor Microcode Network Processor NoC noc OCCN Optimization PLL PrimeTime prt RTL RTOS SNUG STA STMicroelectronics Synopsys Synthesis SystemC SystemVerilog TLM TSMC Verification Verilog Verilog PLI Virtualization VLIW