Intel

Intel Xeon 5500.pdf

http://www.intel.com/technology/ioacceleration/

http://download.intel.com/technology/comms/perfnet/download/98856.pdf

http://nowlab.cse.ohio-state.edu/publications/conf-papers/2007/vaidyana-ispass07.pdf

список файлов:
atoms_price.jpg

http://www.cs.cmu.edu/afs/cs/academic/class/15213-f01/docs/mpr-p6.pdf

список файлов:
mpr-p6.pdf

A sequential scan cell includes an input port for functional data and an input for scan test data. The input for scan test data is an input to a master scan flip-flop coupled to a slave scan flip-flop defining a scan test circuit. Such a scan test circuit is coupled to the functional circuit of the sequential scan cell such that the path for a functional signal is not through the scan test circuit, imparting no performance penalty to the functional signal. Scan test data is scanned in and out of the sequential cell by two non-overlapping scan clocks that are active only when system functional clocks are in an off state.

список файлов:
007437634 Test scan cells.pdf

Operation Description Language на примере IA32 для CALL.

Domain Specific Language for ISS (Code Generation)

список файлов:
ODL.pdf

http://www.rusnano.com/Publication.aspx?PublicationId=1004

Algorithms for VLSI Physical Design Automation

список файлов:
Algorithms for VLSI Physical Design Automation.pdf

список файлов:
etw7B_1_1.pdf

список файлов:
pentium_bug.pdf
pentium4_multi_GHz_clocking.pdf