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e.proydakov прокомментировал PHD

Anton Gerasimov написал PHD, Cisco Nexus 7000, VMWARE: How to beat citrix, Intel Xeon 5500, DDR2 Implementation on 130nm and 90nm designs, NVIDIA C51M Mobile Integrated Graphics Processor, Lenovo mobile AR, Lenovo: IdeaPad, Micron: Overview of DDR3, MindSpeed DSP: Communications Convergence Processor, LDPC benchmarking for DVB-H, NXP: Low-Power WLAN, NXP: NFC General Introduction, Synopsys: Power Reduction, VCS Constraint Debug, MIPS Roadmap

присоединился участник   e.proydakov

Anton Gerasimov написал Network Processors - Architecture, Programming, and Implementation

alexndr.frolov прокомментировал Principles and Practices of Interconnection Networks

Anton Gerasimov написал Principles and Practices of Interconnection Networks

присоединились 2 участника   savinovsv, alexndr.frolov

Anton Gerasimov написал Packet Forwarding Technologies, ESL Models and their Application

присоединились 2 участника   murometz, al1

Anton Gerasimov написал Synthesis And Optimization Of Digital Circuits, Number of power gates

присоединились 2 участника   ya_slavets, producer

Anton Gerasimov написал OMAP, dismissible load, Accelerator Coherency Port, Rainer Leupers; Design Space Exploration, Mailbox for AXI, Calibre YieldAnalizer, Instruction Level Power Modeling, Standard Gotchas, Yield, DFM, Verilog Interview Questions, Retargetable code optimization, Intelligent Energy Manager, MPFPGA, Fault Modeling and Testing of Retention Flip-Flops in Low Power ..., Static and Formal Verification of Power Aware Designs at the RTL Using UPF, DMA for GMAC, TCP HW parser , New Server ARCH, Clock Gating Element, Rapid Prototyping Design Methdology, SMART DMA, eSRAM, HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs, Barrier Synchronization, Virtualization for HPC, Verilog Books; PLL Books, EVE Zebu, Simulation Speed, Design Space Exploration for MPSoC, HAL for SoC; BSP CoWare, BSP, Mapping into the MPSoC; Parallel Modeling, Traffic Shaping in NoC, Exploring ISA, Going Parallel with Prism, Memory Controller Optimizations for Web Servers, Debugging & Verification of Parallel Systems, Low-Power Data Bus Encoding, Degradation Delay Model, Dini Group, MOSIS prototyping, Europractice; Low cost IC prototyping, Divider in PLL Frequency Synthesizer, Divider in PLL Frequency Synthesizer, Design For Logic-Tile, Clock Management on a Multi-Clock Design, Clock Divider, Fundamentals Of Digital Logic With Vhdl Design, Core_tile, PLL Design and Layout, Duty cycle for primary input clocks and pll output clocks, Linux Cortex-A8, Primecells, Self-Refresh Mode; DDR2 Memory Controller, PLL Design, ARM Architecture Reference Manual, Fast Context Switch, ARM Low-Power, mpeg clock recovery, CTS Buffer , Using Encounter for Floorplanning, Placement, and Clock Tree Synthesis, H.264_And_MPEG-4_Video_Compression, Forum FSA, DOCEA, Power States, Arbiter Channel; TLM Modeling, PrimeXsys Platform, PUE DCIE, Asynchronous Circuit Simulation , Parallel and Distributed Simulation Systems, Wrapper, glue, Network Interface Chip, DFT Lab, Video Coding With Superimposed Motion Compensated Signals Applications to H.264 and Beyond, Program Optimization Strategies for Data-Parallel Many-Core Processors, IBM CoreConnect, VCD Generation, DOCEA - High Level Power Optimization, Inside Cisco, Power Planning, HPI, Host Port Interface, Managing Fabless Cost, DFM, Glue Logic, Automatic Layout Modification Including Design Reuse of the Alpha CPU in 0.13 um SOI Technology, Interprocessor Communication, DDR, DDR3 IP, Energy Macro-models, AMBA Power Consumption, Clock Domain Crossing, On-Chip Communication Architectures-System on Chip Interconnect, SDC, STbus Kit, System Level Modeling of an AMBA Bus, Low-Power RAM, eSwitch Design, Julia Dushina (Verification), IC design people3, Traviata Board Debug, Cortex-A8 Synthesis, Interra MC2, Mali GPU , ARM Integration, Mailbox Communication, Mailbox in SystemVerilog, IPC Mailbox, VLIW: old architecture of the new generation, SUN Fire, Aptix, ROUTING, RC Extraction and SSTA, Si2 Member Report, Domino CMOS, Domino Logic, Wireload models, eSRAM compiler, STV8105, On-chip RF Isolation Techniques, Inverter, Power Management for Multimedia Processors, Synchronization Using Mailbox, AMBA3 AXI Asynchronous Bridge, ARM PrimeCell™ DMA Controller (PL080), Encounter Low Power Lab, Altis, Design Planning, Synopsys Flow, Exploration of Communication Strategies for Computation Intensive SoC , Floorplanning flow, Reconfigurable Computing, Enea, Microcode-based Memory BIST, ARM Austin Design Center, STA - HSPICE Correlation, Advanced Timing Analysis, Constraint Translator for Ambit BuildGates Synthesis, set_clock_gating_check, The IDDQ Mystery, FreePDK 45nm Variation-Aware Design Flow, Static Timing Analysis Based Transformations of Super-Complex , DSM for TSMC, Voltage Drop Analysis, razak hossain; High Performance ASIC Design, Denali PureSpec, Working with DDRs in PrimeTime, DRAM Circuit Design, OpenAccess; Constraints, Topological Synthesis of Clock Trees, Minimization of Boolean Trees, SSTA; Virage Logic, Design for next generation ARM; Cortex-A8 power, Xtensa Power, TSMC Design Flow Diagram, ARMs Smallest Thumb (Cortex-M0), Frequency & Leakage evolution from 250nm to 90nm , 64 bit Adder, STNoC Total, Run-Time Distributed Optimization on MP-SoC, Reset, H264, CAVIUM Startup, ASIC Optimization and Design Strategy Using Multiple Vt Devices, Dynamic Power Saving Using SoC Encounter, Magillem and STMicroelectronics Win OCP-IP Co-Contributor of the Year Awards , Memory Design, DDR Memory Controller, Rambus, Cadence's Ambit BuildGates, Crossing Clock Domains, Verification of Cross Clock Domain Protocols, Multi-Clock Domain (Verifying Synchronization), NEC OPENCAD, NEC AppNotes, Bob Colwell, Sorting in the Presence of Branch Prediction and Caches, Async bridge in LMI, 10M Gates, clock domain partitions, Gray Counter, 17n Marinescu Algorithm, STx7100 Advance Datasheet, HDL code analysis for ASICs in mobile systems, NoC Monitoring, Network Processor Chipset, Arithmetic Built-in Self-Test for Embedded System, TLM Bus Interface for ISS, Algorithms for VLSI Physical Design Automation, Model Abstraction For Formal Verification, Parallel and Distributed Simulation Systems, COTSon Simulator, Asynchronous Bridge; clock domain, MDS, CHESS, RTL coding hints, One-hot mux, RTL Coding Styles That Yield Simulation and Synthesis Mismatches, Hadoop Performance with Memcache, 16 core Network on Chip, ARM ISS + SystemC + RTOS, Application-specific User-Level Thread Schedulers, HEMLOCK: HEterogeneous ModeL Of Computation Kernel for SystemC, Design of Cost Efficient Interconnect Processing Units Spidergon STNoC, SystemC Articles, A fast morphological algorithm with unknown word guessing induced ..., Morphological Variation, NoC Congestion Control, CoCentric SystemC Compiler RTL User and Modeling Guide, Validation de mod`eles de syst`emes sur puce en presence d , Distributed SystemC Simulation, OCCN practices, Describing Synthesizable RTL in SystemC, T1, ST's CADS, NoC Synthesis, Development and Performance Evaluation of Networks on Chip, Microarchitecture for Billion-Transistor VLSI Superscalar Processors , A Functional Coverage Prototype for SystemC-based Verification of an AMD chipset design, Intel® I/O Acceleration Technology (Intel® I/OAT), DRAM Cache, TPC-W, TPC-DS benchmarks, Shared L2 Cache, Solaris Internals, Core Kernel Components, Packet Forwarding Technologies, TPC-W benchmark, UltraSPARC T2 Reference Design Kit, Solaris Containers (Zones), OpenVZ, The Design Warriors Guide to FPGAs, Testing of the Cache Memory in the OpenSPARC T1, Amulet NoC, UltraSPARC T2, Algorithmic Skeleton Programming, Developing and Deploying on UltraSPARC-T1, Method and apparatus for changing microcode to be executed in a processor, Nonblocking Assignments, QNoC Router, 57 Gotchas, MapReduce Pattern, Arbitrary Static Task Graph, gprof for OCCN, Wormhole; Virtual Channels, Arteris Danube design flow, Dynamic Optimization System, Digital Design; Frank Vahid, Ultra-Low Leakage (ULL) retention state for Cortex, GaAs MMIC, DDR2 Dynamic Memory Controller, Mobile Low-Power DRAM, Wattch framework

присоединился участник   svtemp

Anton Gerasimov написал Real-Time Realtime Operating Systems-Concept And Implementation, Real-Time Operating Systems, continued & basic Scheduling Theory, An Introduction to Real-Time Operating Systems: Scheduling Theory, Piranha L2 cache, Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration, Operating-System Controlled Network on Chip, OS21 Debugger, Hardware Techniques to Reduce Communication Costs in Multiprocessors, BrookGPU, OCCN NoC, IEEE 1364 Verilog Working Group, Switch in Godson, Atom's Price, Cell Processors, Atom's Power States: C0, C1/2, C4, C6, D-ITG, Distributed Internet Traffic Generator , VCI Protocol, Verification Environment

loktikvj написал CeltIC Tutorial

Anton Gerasimov написал Joshua J. Yi; Simulation Parameters, STRATEGIES FOR BRANCH TARGET BUFFERS, Delayed Branches, Hybrid Instruction Set Selection Process, SuperH Architecture (Total), StrongARM Characteristics, Microcode Development and Debug Overview & Tutorial, Microcode-Based Memory BIST Implementing Modified March Algorithms, ARM11 MPCore, Optimizing Software in C++; SystemC for Synthesis, Pipeline Evaluation; Instruction State, Functional Simulation of the nVidia G80 GPGPU pipeline, Memory Modeling in ESL-RTL Equivalence Checking, RTL Checker Design, A Two-State Methodology for RTL Logic Simulation, State FSMs, Modeling with System Verilog: Synopsys Synthesis Design Flow, Network Processor Configuration, Build and configure the Linux Kernel, Ramdisk and configure for specific hardware, Network Processors; IXP1200, DPI flow in ModelSim, ARM NEON Intrinsics, ModelSim sccom -link, Co-Emulation Modeling Interface (SCE-MI), FRISC-91 (Fast RISC); FRISC Project, Cache Physical Design, DRG-Cache: A Data Retention Gated-Ground Cache for Low Power, Verilog Race Condition, Advanced Verilog Coding, Reconfigurable Computing The Theory and Practice of FPGA-Based Computation, Verilog Coding for Logic Synthesis, Verilog Event Scheduling, ModelSim Verilog PLI, Open Source Verilog, VERILOG-HDL PLI Reference Manual, Zroute Technology in IC Compiler, LusSy, PINAPA Flow, Dynamic_cast, The gHost in the Machine, TRANGO, Direct Access File System, DDR2 for OpenSparc Verification, Manufacturability Aware Design, Nanometer Physical Verification, Model-based Verification and Analysis for 65/45nm Physical Design, POSIX, Principles of Protocol Design, PDU, ASICs....The Course, Design Rule Checking Verification, Synopsys Design Constraints, Detailed Routing Parameter, Virtual Channel Flow Control, Embedded RISC-Microprocessors with Optimized ISA, Cortex-A8, David H. Albonesi, Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches, Energy per Operation in VLIW, Logic Depth per Stage; Optimal Pipeline Depth, VLSI seminar from Jarom

присоединился участник   sdvoretsky

Anton Gerasimov написал ThreadX, Advance Hdlsign Training On Xilinx Fpga, Decomposition And Encoding Of Finite State Machines For Fpga Implementation, ThreadX picokernel, Эволюционные алгоритмы для MOO

присоединился участник   mlen

Anton Gerasimov написал The Wrapper Facade design pattern, Native ISS Integration, IPC for Simulators, SystemC Memory Model, Datapath Verification, Static Branch Prediction, Design Compiler, Large Instruction Window, P6, Intel 45-nm High-K Metal Gate, Verifying Register Renaming, Adapting Cache Line Size to Application Behavior , Computer Arithmetics, Dual-Issue Pipeline, Compiling the uClinux port for LEON, Faults, Virtual Channel, MDES - ADL from Trimaran, Topogaphical Mode, Clock Gating Methodology, ASIC-PIIRIEN SUUNNITTELU, Yield Learning Flow Provides Faster Production Ramp, PLI Checker, TCP/IP for Embedded Systems, uCLinux IPC, Performance Comparison, A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC, SystemC ISS Wrapper, Multiobjective Evolutionary Algorithm, PLL Design, IC Design & Verification, CUDA Gather-Scatter, ARM + Nucleus OS, Boundary-Scan Test - A Practical Approach , Skype Protocol Internals, Telelogic TAU, Discrete-Event Simulation, A new binary floating-point division algorithm and its software implementation on the ST231 processor, ST200 Toolchain, CoWare; ESL Design, Power Model for Nostrum, NoC Design and Analysis. Nostrum NoC Simulation Environment, Assertion Processor, Test Data Generation, ABV Verification in ATI, AMD, Bruce Jacob, BILBO, Intellectual Property and Open Source, Dedicated Toolchain for eSW, BILBO, Abramovici, NoC Testing, System-on-Chip Test Architectures (Systems on Silicon), Open Interface Specifications: GDI and KDI, GPROF, Parametric Model, "FAST: Frequency-Aware Static Timing Analysis", OpenSPARC Internals, Cavium OCTEON Programming, Timing Signoff, Cache Optimization, NoC Synthesis, 65nm SRAM, Synthesis for Manufacturability : a Sanity Check, MOO for Architecture, problem definition, BOOKS, Linux for MicroBlaze, Design & Development; Business Development Procedures, RAMP Blue: A Message-Passing Manycore System as a Design Driver, 0.25um ST / Cadence 4.4.3; Design Environment Support, Revolutionized Advanced DRC Checks and LVS Debug, A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems, Energy-Delay Metrics, Design Space Exploration, A Multiobjective Optimization Model, MO Design-Space Exploration of Embedded Systems, Pareto Optimal Curves, Design Space Exploration, Reduced Energy Consumption in SMP Servers, Clustered VLIW Architectures

loktikvj написал Virtuoso XL Training Manual

Anton Gerasimov написал CADENCE IC, CDNLIVE 2005

loktikvj написал DRACULA Standalone Verification, Layout Editor, IC/ASIC Design Composition and Analysis, Verilog-XL

Anton Gerasimov написал Energy Consumption in SMP Servers, Analysis of Algorithms, OS21 Debug, 45nm CMOS Process from STMicroelectronics, Using POSIX - based RTOS for Embedded Systems, Logic For Computer Science. Foundations of Automatic Theorem Proving, Model Checking, System Validation, Nano-CMOS Circuit and Physical Design, IC Physical Design and Verification-SOC Encounter

loktikvj прокомментировал Cadence Verilog

Anton Gerasimov написал CACTI: A New Cache Design Tool for Pipelined Nanometer Caches, Asynchronous NoC Router Design

loktikvj, Anton Gerasimov прокомментировали Cadence Verilog

Anton Gerasimov написал Asynchronous Test Wrapper for NoC, TIMA Asynchronous Library, The TAST design environment, Ru.Chip Company (Fabless), Q3 2008 Funding Activity