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Fabless IC Design/ Разработка чипов

IC Design Technologies, Search Engine Technologies, Fabless design, processors
     
присоединился участник nagornyhdn
21 августа 2013, 15:31
Dmitry Murzinov прокомментировал RuChip, Russian startup in Moscow
26 августа 2012, 21:06
Anton Gerasimov написал LANDesk-2012. Построение гибких и прозрачных ИТ-процессов в эпоху корпоративной мобильности, Fusion IO, RuChip, Russian startup in Moscow , Лаборатория Пентковского, Continental: Connected cars, wireless communication and networks part5, Cryptographic_Software_Export_Controls_in_the_EU, Telit, NFC, Qisda GSM GPRS, Vimpelcom Flexi EDGE BTS, ZigBee, ORACLE AIRLINE CRM, Telenav, Automotive cookbook, Qt for S60 Mobile Extensions, GPSAGPS Principle and Testing Solution, TI OMAP, ARM Technology Update, 3D solution chip from Movidius, The BEA Virtualization Vision, KPMG Cisco Supply Chain Customer Presentation, Protecting (and Improving) the IP in your IP blocks, BlueCoat for Web Security, RADVISION: 3G Interactive Video Service and Platform, Understanding IPTV Technologies: From Video Compression to IPTV Network Design, Delivering_Highest_Performance_CPE_SOCs_at_the_Lowest_Power_Consumption, Marvell: MMP2 DDR Controller, Kaspersky: Идентификация уникальных паттернов в real-time, Security Update, Sitime company profile, IPSec VPN between NetScreen and Cisco Router, Novelty behind the on-chip transport system, QNX Momentics IDE Integrated Development Environment QNX Software Systems, BlackBerry Marketing, ProLiant G7 AMD Based Server 201012, Syntest, VOIP Introduction - MGCP, Cavium Networks OCTEON Plus CN50XX Hardware Reference Manual, OCTEON, Oracle Exadata, GDDR3 Memory Tuning Guide, Exadata ASM Intro, oracle EXDATA hardware-overview, Nokia W-CDMA channles, Insight into EPON & GPON, Nokia QtWrt, Qualcomm QCT_Bluetooth_FM_OEM_Update_March2009r3, SAP Roadmap, Cisco one bank one architecture, Oracle Finance Architecture Overview, PPT IPO Roadshow PPT Gushan_Presentation_September_2010, Open Enterprise Server 2, Alibaba, Novell IDM, Cloud computing @ Yahoo!, december_29_top_10_strategic_tech_cclaunch, conformal_lec_training_basic_advance, Dell Cloudera Key Strengths, Cisco Supervisor architecture, Tuning Hadoop for Performance, HBase performance and robustness enhancement, Lenovo 2010/11 Annual Results, ASIC accelerated security systems, Basis of VPN Technology, Blue Coat for Web Security, Atmel Touchscreen, Compatibility Test Suite (CTS) Framework User Manual, Touch Screen, Samsung Flash Solution, DDR3, Perfect_Guest_for_Virtual_Machines_presentation_en, PicoChip, VxWorks for Hitachi SuperH, LTE-Femtocell, CloudStack 3.0 Technical Presentation, Intel Atom Roadmap, Network edge security, Teradata in the clouds, Netbackup, Device Modeling Guidelines, JAVAD Navigation, Cisco 7600 QoS Architecture, JDSU 100G, Virtualization with (KVM), Symantec, VMWare, Open Source Business Models, Qualcomm QCT UMTS, The Future of Low Power, Clock Gating Flow, Semicon Russia 2012, Deploying QoS for Cisco IP and Next Generation Networks, MIPS Roadmap, Google OpenFlow, A Guide to Network Processors, Cisco Adapters - 20081010, cisco router7600, RadiSys, RLDRAM Update JULY 11, Cisco Unified Communications 500 Series, IPSec SSL VPN, Cisco Catalyst Switch Guide, Cisco CRS-1 20090703 (NXPowerLite), Huawei NE40E&80E, Juniper Product Portfolio for FSI, DRAM Principle by Qimonda(Tosen), Cisco 6500 Capacity Model v20081128, ФГУП ЭЗАН, Ingenic® Jz4730 Processor, АРХИТЕКТУРА,_ПРОГРАММИРОВАНИЕ_И_ПРИМЕНЕНИЕ_32-РАЗРЯДНЫХ_RISC-МИКРОПРОЦЕССОРОВ_с_архитектурой_MIPS, OCTEON Software Overview, Cisco ASR 1000, IPSec Cisco, IP over DWDM, Juniper-EX8200-vs-Cisco-Nexus-7000, Altera 100G, Fabric ASIC, 40g-100g market window, JUNIPER EX8200 COS, ASR 1000, SERDES, ASR 1000 System Architecture, Competitiveness of FTTH & FTTB, Cisco BGP, Huawei LTE the Next Generation Network Beyond 3G, OptiX PTN 910, Managed and Cloud services Cisco Service Provider GTM, Understanding Network Processors, UTStarcom, cisco live 2010 Bridging in the Data Center With or Without Spanning Tree, Fulcrum, Juniper VPN, Cisco network topology, Huawei security products and solutions, DC ByteZ FabricPath, Network Flow Processing, Catalyst 5000, Cisco Router, CenterFlex Technology, Cavium: Packet processing, Cisco Nexus, QuantumFlow, The_Mathematical_Theory_of_Nonblocking_Switching_Networks, GPRS Routing, IOS Recommendation for 7600, Cisco IOS, Edge core, IC Mask Design Essential Layout Techniques
26 августа 2012, 19:19
присоединился участник Dmitry Murzinov
7 апреля 2012, 15:09
присоединился участник arkadzab
27 марта 2012, 13:19
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Квартальный отчет GONT по капитализации (Отчет К1)
Оценка капитализации GONT на 05.04.2018.
Почему уже сейчас GONT стоит $4M, а будет стоить $1B через 2 года?
https://cloud.mail.ru/public/AAfc/vEsGeYjXz
http://gont.io/
https://t.me/gont_official

http://community.sk.ru/net/1110120/b/news/archive/2013/10/06/kompaniya-ruchip-2013.aspx

06.10.13, 14:13
Автор Anton Gerasimov

RuChip is developing the SMP version of its GOYA core.

This architecture extension is based on a snooping mechanism that exploits the well know MESI protocol, with the aim to leverage the current GOYA implementation and adding to it the capability to support an SMP sub-systems or more simply just to support cache coherency. The target is SoC platforms with a small number of processors that share a coherent memory address space.

The approach described in this document is based on memory coherency managed at the L1 data cache interface with an option of an L2 cache shared between processors to maximize the expected benefits in terms of latency and bandwidth saving/traffic reduction on the system bus, but leaving the choice to use whatever memory hierarchy free for the SoC architect to make. The snooping interconnect defined here can be applied unchanged to different memory hierarchies, the snooping mechanism will remain the same. For example, a coherent multi level private cache subsystem will add complexity to the cache controllers but the unit which manages memory coherency will not be affected by it. This is a desirable property that allows this approach and a big part of the design that’ll come with it to be leveraged for future spins of the GOYA architecture.

http://community.sk.ru/net/1110120/b/news/archive/2013/04/06/goya-smp-core.aspx

http://community.sk.ru/net/1110120/b/news_en/archive/2013/08/10/goya--the-first-processor-of-the-ruchip-company--is-being-calculated-in-cadence-encounter.aspx

“GOYA” First Stage Prototype Scheme (Prototype 2013-2014)

http://ruchip.com/goya_iss/

ключевые слова

The Next Generation of Healthcare: Personal Connected Health & Wellness
Shinsuke Tagami

Connected health.pdf

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Fabless IC Design/ Разработка чипов

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